SerialATA: The Future of Commodity Storage
Overview:
- Quick Specs
- Design: SerialATA Organization
- Design: Signaling and Speeds
- Design: BIOS/CMOS and Drivers
- Technology: Cabling and Power
- Technology: Initial Chipset Implementations
- The Future of SerialATA
Quick Specs
For those that just "want the facts" (without TheBS' verbage) here's how SerialATA (1st gen) is different:
| Speed: | 1.2Gbps (150MBps) |
| Signaling (Analog): | 1.5GHz, 250mV diff |
| Signaling (Digital): | 8/10b encoded, full-duplex TX/RX, 32-bit CRC |
| Channel: | 1 Device per "Port" (period no master/slave) |
| Cable: | 1m max length, one device per cable (period) |
| Connector (Signal): | 7-pin copper shielded (non-twisted) |
| Connector (Power): | 15-pin 3.3/5/12V (optional legacy 4-pin Molex) |
Design:
SerialATA Organization
As the name suggests, Serial AT Attachment (SerialATA) is a serial transfer, aka transfer one bit at a time, technology. It will augment and eventually replace today's current [Parallel] AT Attachment and AT Attachment Peripherial Interfaces (ATA/ATAPI) which use 16-bit wide transfers.
Although it does transfer one bit at time, data is still organized into transfered bytes (8-bits, in a 10-bit encoding) and buffered double-words (32-bits) from the digital standpoint. For those familiar with the OSI model often used in networking, the 4 organization layers of SerialATA are very similar:
| Application: | BIOS and operating system drivers |
| Transport: | sector addressing and 32-bit buffering/FIFO |
| Data Control: | digital transfer layer, 8/10-bit codec, CRC |
| Physical: | analog transfer layer, differential signaling on wire |
Design:
Signaling and Speeds
At the physical level, the first generation of Serial ATA uses a 1.5GHz signal. It uses a 250mV differential to maintain signal quality over its short distance. The signal is direct, point-to-point, with a 100 Ohm resistor at each end. Yes, this means there is only the host controller and a device on its end "port" -- with nothing else on theline (see Cabling and Power below).
At the data control/link level, 8-bit bytes of data are encoded into 10-bit frames. There are different frame types and 32-bit CRCs are used to verify the integrity of the frame. Assuming no overhead, the maximum data transfer rate (DTR) is 1.5GHz signaling * 8/10 encoding = 1.2Gbps = 150MBps. Of course there are costs involved with control and CRC frames.
Sounds a lot like Ethernet, eh? Only no collisions since there are only devices, each at the end of the bus. Furthermore, there are both transmit and receive pairs, so both ends can talk at the same time aka full duplex. Far higher performing than USB at storage and, like parallel ATA versus SCSI, less overhead than FireWire at a cost of flexibility.
Design:
BIOS/CMOS and Drivers
Closer to the software side is the transport layer. For those familiar with the OSI model, you're probably saying "where's the 'network' layer?" Well Serial ATA need not be addressed nor routed because everything is transfered only between the the same two nodes, host and device.
So we skip directly to the transport layer where FIFO buffers are organized around 32-bit double-words addressed to specific sectors. Kinda like a TCP packet going to a specific port at the OSI's transport layer (yes, that is an oversimplification, but still a viable analogy).
Which brings us to the application level. A disk or other SerialATA device on a SerialATA controller's "port" is designed to look like a "master-only" ATA device from the standpoint of the BIOS. And thanks to the Transport layer, it looks like any typical, dumb 32-bit block device like today's common parallel UltraATA disks. That way existing CMOS and Operating System configuration space needs to changed as little as possible to support SerialATA, both on and off-chipset. A two port SerialATA controller can even emulate a single channel, master/slave [parallel] ATA arrangment from the driver standpoint (only without the
bottlenecks).
This also allows for the creation of a variety of different devices. First off, it makes it easier create a chipset with both SerialATA and [parallel] ATA support**, and then "pin out" to connectors whatever option is desired on the mainboard while still using the same BIOS/CMOS. Secondly, SerialATA-to-[Parallel]ATA bridges are easy to create with minimal logic changes, so SerialATA devices can be sued on existing [parallel] ATA channels (although only 1 device per channel).
SerialATA, of course, has its own registers and other programming interfaces, so it is not completely transparent for mainboard manufacturers and BIOS and driver developers though.
Technology:
Cabling and Power
Okay, enough design talk, let's talk about what you see. The cable. SerialATA, like existing parallel ATA, uses separate cables for data and power.
Along with a 7-pin data cable, a new 15-pin power cable is introduced. This cable provides 3.3, 5 and 12V lines for the device. The addition of 3.3V to the device improves power and thermal efficiency. The 7 + 15 data and power connector has a strictly aligned form-factor which will bring about a standardized "hot-swap" configuration, akin to single connector attachment (SCA) used for SCSI.
Optionally, drive manufacturer's can include a legacy, 5/12V, 4-pin Molex power connector. This can be done either in addition to or as a replacement for the newer 15-pin SerialATA power connector. First generation drives will probably ship with both, although many might ship with only a legacy Molex connector instead.
Technology:
Initial Chipset Implementations
For the most part, early SerialATA adopters will be using off-chipset, add-in SerialATA controllers -- either on-mainboard or on an add-in PCI/PCI-X card. From the standpoint of BIOS, POST and operating system, the extra chips or cards will be no different than any other add-in [parallel] ATA or SCSI host adapter. They will have their own configuration menu, Int13h BIOS services, etc... BIOS Disk IDs (and boot priority) will be assigned no differently, 80h, 81h, etc... all separate from the on-chipset ATA channels (depending on the BIOS/CMOS settings, as before). Several new mainboards are already being marketed with Promise, High-Point Technologies and other off-chipset SerialATA controllers on them.
This is a very natural approach since their are still a maximum of 4 devices, which makes BIOS/CMOS configuration issues simple for technicians. Only now the first two devices operate independently from each other in the hardware (unlike [parallel] ATA master/slave), so there are no more worries about performance issues when both "ports." are used. At the same time, there is still a legacy [parallel] ATA channel available for legacy optical devices. Since optical device performance is far, far less, two optical devices in a aster/slave combination is usually not a bottleneck. So even in the first generation of Serial/Parallel hybrid ATA chipsets, upto 2 hard drives and 2 optical devices can be used just on the chipset's southbridge without fear of performance issues!
The Future of SerialATA
On the speed front, 3 and 6GHz SerialATA signaling is already in development. SerialATA II will work on the same cabling as the first generation, but deliver speeds upto 2.4Gbps (300MBps). Beyond that, shield twisted pair (STP) cabling will probably be used for 4.8Gbps (600MBps) and faster for SerialATA. The new SerialATA II spec is being written to guarantee that 2nd generation drives will be upward compatible with any cabling and configuration changes for those higher speeds. At that time, at least one set of first generation SerialATA ports will probably remain for older, slower devices on the same chipset as those with 3rd+ generation primary storage devices.
